A conventional synchronous type semiconductor memory is disclosed in Japanese Laid-Open Patent Publication No. 61-39295 and No. 62-275384.
The synchronous type semiconductor memory has a memory cell array in which memory cells are arranged in rows and columns.
A decoder is coupled to an input of the memory cell array. A latch circuit and an output buffer are coupled to an output of the memory cell array. When data is read from the memory cell array, externally generated input addresses are decoded by a decoder so that one of the memory cells is selected in the memory cell array. Data stored in the thus selected memory cell is latched temporarily in the latch circuit. The data latched being synchronized with a synchronous clock is thereafter read out via the output buffer. In a synchronous type static random access memory (hereinafter referred to as SRAM), one pulse alone of a synchronous clock is supplied to the output buffer during a memory access time so that the read data can be accurately output in synchronism with the clock pulse. access starting time to the time when the latch completion signal is generated, and a delay clock number output circuit for outputting the output of the clock counter circuit to an external device.
A second aspect of the present invention comprises a DRAM which selects a memory cell by decoding an address and performs writing data in or reading data from the memory cell, wherein the DRAM further comprises a data latch circuit for latching the data read from the memory cell, an output clock delay control circuit for generating an output control signal.,in response to the number of delay clocks which are set by a synchronous clock and an external input signal, and an output circuit for outputting the read data, which is latched by the data latch circuit, in response to the output control signal.